SRIS Module · CSTL

时序逻辑控制综合

将时序规格编译为可执行反馈策略、参考调节器与基于优化的监督器,实现构造性安全控制。

STLSafe ControlVerification
01
Barrier Functions
02
Reference Governors
03
Closed-Loop Guarantees
SRIS实验室SCUT · GZIC
智能、可靠、可解释系统
Overview

研究范围

时序逻辑控制综合是SRIS研究体系的核心模块之一。它连接方法、模型与部署场景,使理论、算法与系统级成果能够形成统一的学术叙事。

Control & STLSystems verification机器人
Integration note. The six uploaded modular files were integrated into the website as navigable module pages. Their presentation now matches the unified SRIS visual system and links directly to the broader Research, People, Publications, and Gallery sections.
代表性成果

相关论文

代表性论文从当前成果归档中提取并嵌入此处,使每个模块页面同时具备视觉入口与下方论文列表。

浏览全部成果

Collaborative design of fault diagnosis and fault tolerance control under nested signal temporal logic specifications

Penghong Lu, Gang Chen, Peng Wei, Rong Su
IEEE Transactions on Automation Science and Engineering, 2, 2026
期刊
Signal Temporal Logic (STL) is widely used for specifying complex time-dependent behaviors in cyber-physical systems (CPSs), particularly in safety-critical domains. However, fault diagnosis (FD) and fault tolerant control (FTC) under nested STL (NSTL) specifications remain challenging, especially for nonlinear systems. This paper proposes a collaborative design (CoD) framework that jointly integrates FD and FTC under NSTL constraints to enhance detection accuracy and ensure robust system performance. First, a fault detection observer is developed by constructing fault tolerant feasible sets that can predict whether ongoing system trajectories satisfy NSTL specifications. To address the feasibility issue in real-time control synthesis, we introduce the concept of fault tolerant control with recursive feasibility (FTCRF), enabling the controller to maintain constraint satisfaction and system stability even under faults. A model predictive control scheme guided by control barrier functions (CBFs) ensures safe trajectory tracking within specified bounds. Simulation studies on single integrator and unicycle models demonstrate the effectiveness of the proposed method in accurately detecting faults and maintaining task satisfaction under NSTL constraints. Note to Practitioners—This work is motivated by the need for robust fault management in safety-critical cyber-physical systems such as autonomous vehicles, smart manufacturing systems, and robotic healthcare platforms. In these environments, rapid and accurate fault diagnosis—alongside continued safe operation despite faults—is essential to prevent downtime and maintain system integrity. Our proposed framework provides a practical methodology to jointly design fault detection and control strategies, explicitly accounting for complex temporal task constraints specified using nested Signal Temporal Logic. The key contribution is the collaborative integration of a fault diagnosis observer with a fault tolerant controller based on recursive feasibility, ensuring that the system can continue operating safely even when faults occur. Moreover, the use of STL Trees (STLTs) provides a tractable means of reasoning over complex time-based specifications. Practitioners can adopt this framework to improve system reliability, reduce intervention costs, and ensure compliance with temporal task requirements in dynamic and uncertain environments.

Decomposition-Based MPC for Uncertain Systems With Nested Signal Temporal Logic Specifications

Jiarui Zhang, Penghong Lu, Gang Chen
IEEE Control Systems Letters, 9, 2025
期刊
We study control synthesis for uncertain systems subject to nested STL tasks and propose a decomposition-based MPC framework. The method resolves nested specifications into atomic subtasks and combines them with distributed shrinking-horizon MPC to improve tractability and control performance under bounded disturbances.

Control/Physical Systems Co-design with Spectral Temporal Logic Specifications and Its Applications to MEMS

Gang Chen, Zhaodan Kong, Longhan Xie
International Journal of Control, 2024
期刊
We study control/physical co-design for LPV systems with spectral temporal logic specifications. By transforming spectral-temporal requirements into mixed-integer matrix inequality constraints, the paper develops an iterative optimization framework and demonstrates its effectiveness on MEMS applications.
Position in the lab

该模块在SRIS研究体系中的位置

模块定位
Control Synthesis with Temporal Logic is presented as a reusable research block that can connect to papers, projects, talks, and demonstrations across the website.
Typical outputs
This module can aggregate theory papers, application case studies, tutorial materials, project narratives, and visual evidence under one stable page structure.
关联入口
使用下方快速入口,从当前模块页面跳转至研究概览、团队页面、成果列表与实验室视觉内容。
Related themes

关联关系

  • Control & STL
  • Systems verification
  • 机器人